This invention relates to a binary logic circuit for determining a ratio
      div    =          x      d        ,particularly for the case in which x is an unsigned variable integer and d is a positive integer constant of the form 2n±1.
It is a common requirement in digital circuits that hardware is provided for calculating a ratio
  x  dfor some input x, where d is some constant known at design time. Such calculations are frequently performed and it is important to be able to perform them as quickly as possible in digital logic so as to not introduce delay into the critical path of the circuit.
Binary logic circuits for calculating a ratio
  x  dare well known. For example, circuit design is often performed using tools which generate circuit designs at the register-transfer level (RTL) from libraries of logic units which would typically include a logic unit for calculating a ratio
      x    d    .Such standard logic units will rarely represent the most efficient logic for calculating
  x  din terms of circuit area consumed or the amount of delay introduced into the critical path.
Conventional logic for calculating a ratio
  x  dtypically operates in one of two ways. A first approach is to evaluate the ratio according to a process of long division. This approach can be relatively efficient in terms of silicon area consumption but requires w−n+1 sequential operations which introduce considerable latency, where w is the bit length of x. A second approach is to evaluate the ratio by multiplying the input variable x by a reciprocal:
                              x                                    2              n                        -            1                          =                              x            ·                          1                                                2                  n                                -                1                                              =                      x            ·            c                                              (        1        )            
Thus the division of variable x by 2n−1 may be performed using conventional binary multiplier logic arranged to multiply the variable x by a constant c evaluated at design time. This approach can offer low latency but requires a large silicon area.